Various approaches are available for transmitting memory addresses from a central processing unit (CPU) to a memory array comprising a plurality of DRAMs. For example, in the case of linear addressing, the address bits from the CPU address bus are latched by latching registers as row addresses (RA) and column addresses (CA) and are multiplexed out on the memory address (MA) bus to the memory array. An address selector multiplexes either row addresses (RA) or column addresses (CA), depending on which strobe (row address strobe or column address strobe) is actuated. In the linear addressing case, the memory address lines are dependent upon the current CPU address. In another case, the memory address lines can be selected by information contained in the interleave mode and the memory map set-up. In this case, which is referred to as "static" memory address decoding, the desired functions are selected by the user by writing into configuration registers to define the type of interleave (word or block) desired and to select the memory map to be utilized. Each of the foregoing approaches has inherent disadvantages in that it cannot be utilized when memory maps support mixed DRAM sizes. For example, when utilizing a controller that can support four banks of DRAMs, with each DRAM bank including three sizes of DRAMs, twenty-five (25) different memory map options are available and many of these options include different DRAM sizes. It has been found that fifteen (15) of these memory map options cannot be implemented by the aforementioned prior art approaches. These unsupported memory map options are those which include mixed DRAM sizes and all three bank options.
Because the prior art approaches cannot be utilized to implement particular memory map options, it has become desirable to develop a method and apparatus for dynamically decoding the current CPU address without input from the user as to type of interleaving required and/or the memory map option desired.